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• Should have worked on Front end design,Synthesis and timing skills is must. • Should have good background on timing closure. • Hands-on experience on front end and timing tools -EDA tools for ASIC - Synopsys or Cadence- is a must. |
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• Verification environment development at Module and SoC Level • OVM / VMM based Methodology with strong understanding of OOPs concepts • Expertise in Test Plan development & its execution • Expertise to write Assertions • Strong Simulation & Debugging skills • Scripting abilities with Perl , Shell Scripts etc., |
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